In the semiconductor device which is intended for, for example, the power semiconductor module, with an increase in current capacity and the density of components and a reduction in the size of the module, the amount of current flowing through wiring lines in the package has increased and it is necessary to improve the radiation performance of the module. In addition, in many cases, a lead frame using a copper plate is used, instead of aluminum wire bonding according to the related art, in order to reduce wiring inductance.
FIGS. 8(A), 8(B) are a vertical cross-sectional view and a plan view illustrating a semiconductor device according to the related art. FIG. 8(A) is a vertical cross-sectional view taken along the line A-A of FIG. 8(B). An insulating substrate made of, for example, ceramic is a DBC (Direct Bonding Copper) substrate having conductor patterns 2a, 2b bonded to both surfaces thereof. In addition, a semiconductor chip 3 is mounted on the conductor pattern 2a which is formed as a copper circuit on the front surface of the insulating substrate 1 by soldering. The conductor pattern 2b which has the same thickness as the conductor pattern 2a and is bonded to the rear surface of the insulating substrate 1 is bonded to a heat-dissipating base member 4 to dissipate heat generated from the semiconductor chip 3 to the outside. The heat-dissipating base member 4 forms the bottom of a resin case 5 and two large and small insulating substrates 1 are bonded to the heat-dissipating base member 4. The semiconductor chip 3, an internal connection terminal 7, and an aluminum wire 8 are protected by a gel-like sealing member 6 which is filled in the resin case 5.
FIG. 8(B) is a plan view illustrating the state of the semiconductor device before the sealing member 6 is filled. Metal electrodes 3a, 3b of the semiconductor chip 3 are internally wired to predetermined portions of the conductor pattern 2a by the internal connection terminal 7 and the aluminum wire 8. In addition, a plurality of external lead terminals 9a, 9b is drawn from the conductor pattern 2a to the upper surface of the resin case 5. The internal connection terminal 7 and the external lead terminals 9a, 9b are lead frames obtained by processing copper plates.
In the semiconductor device, such as a module-type power semiconductor device, an intelligent power module, or a discrete semiconductor product, the metal electrodes 3a, 3b of the semiconductor chip 3 and the internal connection terminal 7 and also the internal connection terminal 7 and the conductor pattern 2a fixed to the insulating substrate 1 are wired inside the device, and the external lead terminals 9a, 9b are drawn to the outside of the device. In the semiconductor device, in general, the semiconductor chip 3 and the conductor pattern 2a, the conductor pattern 2b and the heat-dissipating base member 4, or the conductor pattern 2a and the internal connection terminal 7 or the external lead terminals 9a, 9b are connected to be wired by, for example, soldering, brazing, ultrasonic bonding, or laser welding. In addition, in general, components of the semiconductor device have a square shape or a rectangular shape and are formed by bonding metal materials with different thermal expansion coefficients.
FIG. 9 is a cross-sectional view illustrating the semiconductor device according to the related art taken along the line IX-IX of FIG. 8(A).
In the semiconductor device intended for, for example, a power semiconductor module, in general, the conductor pattern 2b bonded to the heat-dissipating base member 4 has a square shape or a rectangular shape, as illustrated in FIG. 9. In addition, in general, when a wiring line is formed between a semiconductor chip and a metal terminal, between metal materials, or between the metal terminal and a metal pattern fixed to an insulating substrate, each of the components which are connected to each other has a shape corresponding to the outer shape of the module and has a square shape or a rectangular shape. Therefore, when the semiconductor chip and the metal terminal, or metal materials with different thermal expansion coefficients are connected to each other by soldering or brazing, the components have different thermal expansion coefficients in, for example, the temperature cycle reliability test and stress which occurs along the bonding surface is concentrated on an angular corner. Therefore, a solder layer or a brazing filler metal layer is likely to be broken or cracked.
FIGS. 10(A), 10(B) are diagrams illustrating a crack which occurs in a solder fixing layer in the temperature cycle test. FIGS. 10(A), 10(B) illustrate cracks which occur when components are repeatedly expanded and contracted in, for example, the temperature cycle reliability test in a state in which the conductor patterns 2b formed on the rear surfaces of the two large and small insulating substrates 1 illustrated in FIGS. 8(A), 8(B) are fixed to the heat-dissipating base member 4 by soldering.
In FIGS. 10(A) and 10(B), the progression direction of the crack which occurs in each of the fixing layers 13a, 13b is represented by an arrow. In the ultrasound picture of the fixing layer 13a illustrated in FIG. 10(A) which has a square shape in a plan view, a region corresponding to a portion of the solder in which a crack occurs is represented as a large white region.
As above, in the semiconductor device in which the lower surface of the conductor pattern 2b corresponding to the metal member 12 illustrated in FIG. 10 is soldered to the heat-dissipating base member 4 corresponding to the metal member 11, a large shear strain occurs at the corners of the fixing layer 13, which causes a crack to occur from the corners. When the crack occurred at the corners of the insulating substrate 1 reaches a bonding surface to the semiconductor chip 3, a heat flux from the insulating substrate 1 to the heat-dissipating base member 4 is blocked by the crack. Therefore, the radiation performance of the semiconductor chip 3 for radiating the generated heat deteriorates. As a result, the junction temperature of an element abnormally increases, which leads to thermal fracture.
The following Patent Document 1 discloses a semiconductor device with the following connection structure. When the thickness of a solder layer is small, fatigue breakdown occurs rapidly due to thermal stress which is applied to a soldering portion due to the difference in thermal expansion between an insulating substrate and a lead frame due to a heat cycle in a usage environment. Therefore, a protrusion is formed on a soldering surface of the copper circuit pattern of the lead frame or the insulating substrate to prevent a variation in the thickness of the solder layer.
Furthermore, Patent Document 2 discloses a structure in which, in order to reduce stress applied to a bonding portion, chamfered portions are formed at four corners of a substrate or a slit is formed in a conductor pattern. In this structure, thermal stress which is applied to the bonding portion due to a thermal cycle is reduced to increase the time until a crack occurs, thereby preventing the growth of the crack.